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| author | Jannis Harder <me@jix.one> | 2022-12-21 14:42:34 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2023-01-11 18:07:16 +0100 |
| commit | 1494cfff001bd23ee1bcd5dbfe1ee04dded25ac4 (patch) | |
| tree | 255d3245f8546694dc91d7245d4c1eeeed817491 /kernel/celledges.cc | |
| parent | f6458bab702e08ade0c15d7f7d8580cb5463d685 (diff) | |
| download | yosys-1494cfff001bd23ee1bcd5dbfe1ee04dded25ac4.tar.gz yosys-1494cfff001bd23ee1bcd5dbfe1ee04dded25ac4.tar.bz2 yosys-1494cfff001bd23ee1bcd5dbfe1ee04dded25ac4.zip | |
New kernel/yw.{h,cc} to support reading Yosys witness files
This contains parsing code as well as generic routines to associate the
hierarchical signals paths within a Yosys witness file to a loaded RTLIL
design, including support for memories.
Diffstat (limited to 'kernel/celledges.cc')
0 files changed, 0 insertions, 0 deletions