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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-19 10:50:32 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-19 10:50:32 +0200 |
| commit | eb3b9fb24ac6547caa5d4063e61be600fc0d55f5 (patch) | |
| tree | ffb26ba622ba97a52865bdb47002663a23d88df2 /kernel/cellaigs.h | |
| parent | 64947453e22404e570d670416ad66511a799e666 (diff) | |
| parent | addf01d45dd795b4fe711012facbe43dd7c2eae7 (diff) | |
| download | yosys-eb3b9fb24ac6547caa5d4063e61be600fc0d55f5.tar.gz yosys-eb3b9fb24ac6547caa5d4063e61be600fc0d55f5.tar.bz2 yosys-eb3b9fb24ac6547caa5d4063e61be600fc0d55f5.zip | |
Merge pull request #1104 from whitequark/case-semantics
Clarify switch/case semantics in RTLIL
Diffstat (limited to 'kernel/cellaigs.h')
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