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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-28 20:27:27 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-28 20:27:27 -0800 |
| commit | a82a7eb42e4d7059ff6efa89b1013134015e118a (patch) | |
| tree | c3df467bd0600ec04e1531414841f2f967c95652 /kernel/cellaigs.h | |
| parent | b84febafd75bc66d64cdc573265e086800b3e420 (diff) | |
| parent | cd2902ab1fec57503320e32ba5620c6487f9cb85 (diff) | |
| download | yosys-a82a7eb42e4d7059ff6efa89b1013134015e118a.tar.gz yosys-a82a7eb42e4d7059ff6efa89b1013134015e118a.tar.bz2 yosys-a82a7eb42e4d7059ff6efa89b1013134015e118a.zip | |
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
Diffstat (limited to 'kernel/cellaigs.h')
0 files changed, 0 insertions, 0 deletions