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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
| commit | c094c53de83707a5bf1b268640283f1dde235873 (patch) | |
| tree | 27e480f63e0d34d8cbfcf8fcf29472c198381296 /kernel/bitpattern.h | |
| parent | 8fd8e4a468fb650fe5dcbe892c07010f627e2c2b (diff) | |
| download | yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.gz yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.bz2 yosys-c094c53de83707a5bf1b268640283f1dde235873.zip | |
Removed RTLIL::SigSpec::optimize()
Diffstat (limited to 'kernel/bitpattern.h')
| -rw-r--r-- | kernel/bitpattern.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 934796d24..4f4bc37a0 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -34,10 +34,8 @@ struct BitPatternPool width = sig.size(); if (width > 0) { std::vector<RTLIL::State> pattern(width); - sig.optimize(); for (int i = 0; i < width; i++) { RTLIL::SigSpec s = sig.extract(i, 1); - s.optimize(); assert(s.chunks().size() == 1); if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1) pattern[i] = s.chunks()[0].data.bits[0]; @@ -61,7 +59,6 @@ struct BitPatternPool bits_t sig2bits(RTLIL::SigSpec sig) { - sig.optimize(); assert(sig.is_fully_const()); assert(sig.chunks().size() == 1); bits_t bits = sig.chunks()[0].data.bits; |