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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 19:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | a233762a815fc180b371f699e865a7d7aed77bca (patch) | |
| tree | 722e54921bbc09595c046c6045cd531445945fc9 /kernel/bitpattern.h | |
| parent | 3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff) | |
| download | yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.gz yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.bz2 yosys-a233762a815fc180b371f699e865a7d7aed77bca.zip | |
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'kernel/bitpattern.h')
| -rw-r--r-- | kernel/bitpattern.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index aaefa50fc..0ca26bb34 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -31,16 +31,16 @@ struct BitPatternPool BitPatternPool(RTLIL::SigSpec sig) { - width = sig.width; + width = sig.__width; if (width > 0) { std::vector<RTLIL::State> pattern(width); sig.optimize(); for (int i = 0; i < width; i++) { RTLIL::SigSpec s = sig.extract(i, 1); s.optimize(); - assert(s.chunks.size() == 1); - if (s.chunks[0].wire == NULL && s.chunks[0].data.bits[0] <= RTLIL::State::S1) - pattern[i] = s.chunks[0].data.bits[0]; + assert(s.__chunks.size() == 1); + if (s.__chunks[0].wire == NULL && s.__chunks[0].data.bits[0] <= RTLIL::State::S1) + pattern[i] = s.__chunks[0].data.bits[0]; else pattern[i] = RTLIL::State::Sa; } @@ -63,8 +63,8 @@ struct BitPatternPool { sig.optimize(); assert(sig.is_fully_const()); - assert(sig.chunks.size() == 1); - bits_t bits = sig.chunks[0].data.bits; + assert(sig.__chunks.size() == 1); + bits_t bits = sig.__chunks[0].data.bits; for (auto &b : bits) if (b > RTLIL::State::S1) b = RTLIL::State::Sa; |