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| author | Miodrag Milanovic <mmicko@gmail.com> | 2020-06-24 11:01:06 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2020-06-24 11:01:06 +0200 |
| commit | f993d1875565c329689815a3bf63c6db76774c15 (patch) | |
| tree | 6b59b0ef523527e49424012eaa8ac3b4ecdd441f /frontends | |
| parent | 0835a86e30fc2a934f5e6c96b28c90b59654ed92 (diff) | |
| download | yosys-f993d1875565c329689815a3bf63c6db76774c15.tar.gz yosys-f993d1875565c329689815a3bf63c6db76774c15.tar.bz2 yosys-f993d1875565c329689815a3bf63c6db76774c15.zip | |
verific - import attributes for net buses as well
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 1630c57bc..89d734c40 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1109,7 +1109,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size()); wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex()); - import_attributes(wire->attributes, netbus, nl); + MapIter mibus; + FOREACH_NET_OF_NETBUS(netbus, mibus, net) { + import_attributes(wire->attributes, net, nl); + } RTLIL::Const initval = Const(State::Sx, GetSize(wire)); bool initval_valid = false; |