Merge remote-tracking branch 'origin/master' into xc7dsp

2 files changed, 43 insertions, 21 deletions

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 2e1fb8fad..a8d5abc1e 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -430,6 +430,7 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 			else if (c == 'r') {
 				uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
 				flopNum = parse_xaiger_literal(f);
+				log_debug("flopNum: %u\n", flopNum);
 				log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
 				f.ignore(flopNum * sizeof(uint32_t));
 			}
@@ -496,8 +497,7 @@ void AigerReader::parse_aiger_ascii()
 
 	// Parse latches
 	RTLIL::Wire *clk_wire = nullptr;
-	if (L > 0) {
-		log_assert(clk_name != "");
+	if (L > 0 && !clk_name.empty()) {
 		clk_wire = module->wire(clk_name);
 		log_assert(!clk_wire);
 		log_debug2("Creating %s\n", clk_name.c_str());
@@ -513,7 +513,10 @@ void AigerReader::parse_aiger_ascii()
 		RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
 		RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
 
-		module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
+		if (clk_wire)
+			module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
+		else
+			module->addFfGate(NEW_ID, d_wire, q_wire);
 
 		// Reset logic is optional in AIGER 1.9
 		if (f.peek() == ' ') {
@@ -621,8 +624,7 @@ void AigerReader::parse_aiger_binary()
 
 	// Parse latches
 	RTLIL::Wire *clk_wire = nullptr;
-	if (L > 0) {
-		log_assert(clk_name != "");
+	if (L > 0 && !clk_name.empty()) {
 		clk_wire = module->wire(clk_name);
 		log_assert(!clk_wire);
 		log_debug2("Creating %s\n", clk_name.c_str());
@@ -638,7 +640,10 @@ void AigerReader::parse_aiger_binary()
 		RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
 		RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
 
-		module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
+		if (clk_wire)
+			module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
+		else
+			module->addFf(NEW_ID, d_wire, q_wire);
 
 		// Reset logic is optional in AIGER 1.9
 		if (f.peek() == ' ') {
@@ -776,19 +781,19 @@ void AigerReader::post_process()
 		// NB: Assume box_module->ports are sorted alphabetically
 		//     (as RTLIL::Module::fixup_ports() would do)
 		for (auto port_name : box_module->ports) {
-			RTLIL::Wire* w = box_module->wire(port_name);
-			log_assert(w);
+			RTLIL::Wire* port = box_module->wire(port_name);
+			log_assert(port);
 			RTLIL::SigSpec rhs;
-			RTLIL::Wire* wire = nullptr;
-			for (int i = 0; i < GetSize(w); i++) {
-				if (w->port_input) {
+			for (int i = 0; i < GetSize(port); i++) {
+				RTLIL::Wire* wire = nullptr;
+				if (port->port_input) {
 					log_assert(co_count < outputs.size());
 					wire = outputs[co_count++];
 					log_assert(wire);
 					log_assert(wire->port_output);
 					wire->port_output = false;
 				}
-				if (w->port_output) {
+				if (port->port_output) {
 					log_assert((piNum + ci_count) < inputs.size());
 					wire = inputs[piNum + ci_count++];
 					log_assert(wire);
@@ -797,6 +802,7 @@ void AigerReader::post_process()
 				}
 				rhs.append(wire);
 			}
+
 			cell->setPort(port_name, rhs);
 		}
 	}
@@ -814,6 +820,7 @@ void AigerReader::post_process()
 				RTLIL::Wire* wire = inputs[variable];
 				log_assert(wire);
 				log_assert(wire->port_input);
+				log_debug("Renaming input %s", log_id(wire));
 
 				if (index == 0) {
 					// Cope with the fact that a CI might be identical
@@ -840,6 +847,7 @@ void AigerReader::post_process()
 						wire->port_input = false;
 					}
 				}
+				log_debug(" -> %s\n", log_id(wire));
 			}
 			else if (type == "output") {
 				log_assert(static_cast<unsigned>(variable + co_count) < outputs.size());
@@ -850,6 +858,7 @@ void AigerReader::post_process()
 					wire->port_output = false;
 					continue;
 				}
+				log_debug("Renaming output %s", log_id(wire));
 
 				if (index == 0) {
 					// Cope with the fact that a CO might be identical
@@ -871,6 +880,7 @@ void AigerReader::post_process()
 					else {
 						wire->port_output = false;
 						module->connect(wire, existing);
+						wire = existing;
 					}
 				}
 				else if (index > 0) {
@@ -896,6 +906,7 @@ void AigerReader::post_process()
 						wire->port_output = false;
 					}
 				}
+				log_debug(" -> %s\n", log_id(wire));
 			}
 			else if (type == "box") {
 				RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
@@ -1004,8 +1015,8 @@ struct AigerFrontend : public Frontend {
 		log("        Name of module to be created (default: <filename>)\n");
 		log("\n");
 		log("    -clk_name <wire_name>\n");
-		log("        AIGER latches to be transformed into posedge DFFs clocked by wire of");
-		log("        this name (default: clk)\n");
+		log("        If specified, AIGER latches to be transformed into $_DFF_P_ cells\n");
+		log("        clocked by wire of this name. Otherwise, $_FF_ cells will be used.\n");
 		log("\n");
 		log("    -map <filename>\n");
 		log("        read file with port and latch symbols\n");
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 86dd80c65..52fcf3ee7 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1530,10 +1530,16 @@ skip_dynamic_range_lvalue_expansion:;
 		current_scope[wire_en->str] = wire_en;
 		while (wire_en->simplify(true, false, false, 1, -1, false, false)) { }
 
-		std::vector<RTLIL::State> x_bit;
-		x_bit.push_back(RTLIL::State::Sx);
+		AstNode *check_defval;
+		if (type == AST_LIVE || type == AST_FAIR) {
+			check_defval = new AstNode(AST_REDUCE_BOOL, children[0]->clone());
+		} else {
+			std::vector<RTLIL::State> x_bit;
+			x_bit.push_back(RTLIL::State::Sx);
+			check_defval = mkconst_bits(x_bit, false);
+		}
 
-		AstNode *assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bit, false));
+		AstNode *assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), check_defval);
 		assign_check->children[0]->str = id_check;
 		assign_check->children[0]->was_checked = true;
 
@@ -1546,9 +1552,13 @@ skip_dynamic_range_lvalue_expansion:;
 		default_signals->children.push_back(assign_en);
 		current_top_block->children.insert(current_top_block->children.begin(), default_signals);
 
-		assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_REDUCE_BOOL, children[0]->clone()));
-		assign_check->children[0]->str = id_check;
-		assign_check->children[0]->was_checked = true;
+		if (type == AST_LIVE || type == AST_FAIR) {
+			assign_check = nullptr;
+		} else {
+			assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_REDUCE_BOOL, children[0]->clone()));
+			assign_check->children[0]->str = id_check;
+			assign_check->children[0]->was_checked = true;
+		}
 
 		if (current_always == nullptr || current_always->type != AST_INITIAL) {
 			assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(1, false, 1));
@@ -1560,7 +1570,8 @@ skip_dynamic_range_lvalue_expansion:;
 		assign_en->children[0]->was_checked = true;
 
 		newNode = new AstNode(AST_BLOCK);
-		newNode->children.push_back(assign_check);
+		if (assign_check != nullptr)
+			newNode->children.push_back(assign_check);
 		newNode->children.push_back(assign_en);
 
 		AstNode *assertnode = new AstNode(type);