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authorKamil Rakoczy <krakoczy@antmicro.com>2020-07-10 09:59:48 +0200
committerKamil Rakoczy <krakoczy@antmicro.com>2020-07-10 09:59:48 +0200
commitde649b91943816149e28a49acb4718e41be2589f (patch)
tree88bce35bfb00ef28970a71c2188dff498b0add8d /frontends
parentc0bcbe1f6254f050207a91506a63aa9d784bd8d6 (diff)
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Revert "Revert PRs #2203 and #2244."
This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
Diffstat (limited to 'frontends')
-rw-r--r--frontends/verilog/verilog_parser.y29
1 files changed, 19 insertions, 10 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 0fdf2b516..dfdb11cf0 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -747,7 +747,7 @@ module_body:
module_body_stmt:
task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
enum_decl | struct_decl |
- always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
+ always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';';
checker_decl:
TOK_CHECKER TOK_ID ';' {
@@ -1331,36 +1331,45 @@ ignspec_id:
param_signed:
TOK_SIGNED {
astbuf1->is_signed = true;
+ } | TOK_UNSIGNED {
+ astbuf1->is_signed = false;
} | /* empty */;
param_integer:
TOK_INTEGER {
- if (astbuf1->children.size() != 1)
- frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
astbuf1->children.push_back(new AstNode(AST_RANGE));
astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
astbuf1->is_signed = true;
- } | /* empty */;
+ }
param_real:
TOK_REAL {
- if (astbuf1->children.size() != 1)
- frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
astbuf1->children.push_back(new AstNode(AST_REALVALUE));
- } | /* empty */;
+ }
+
+param_logic:
+ TOK_LOGIC {
+ // SV LRM 6.11, Table 6-8: logic -- 4-state, user-defined vector size, unsigned
+ astbuf1->is_signed = false;
+ astbuf1->is_logic = true;
+ }
param_range:
range {
if ($1 != NULL) {
- if (astbuf1->children.size() != 1)
- frontend_verilog_yyerror("integer/real parameters should not have a range.");
astbuf1->children.push_back($1);
}
};
+param_integer_type: param_integer param_signed
+param_range_type: type_vec param_signed param_range
+param_implicit_type: param_signed param_range
+
+param_integer_vector_type: param_logic param_signed param_range
+
param_type:
- param_signed param_integer param_real param_range |
+ param_integer_type | param_integer_vector_type | param_real | param_range_type | param_implicit_type |
hierarchical_type_id {
astbuf1->is_custom_type = true;
astbuf1->children.push_back(new AstNode(AST_WIRETYPE));