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authorMiodrag Milanović <mmicko@gmail.com>2022-04-18 09:09:36 +0200
committerGitHub <noreply@github.com>2022-04-18 09:09:36 +0200
commitd23260d381a1b58ff7f0a0ce65e1884e2ceaa05d (patch)
tree1eb6aa16dbd750800dd4a10f68336d105da0644c /frontends
parent36b5caf8217d4ca57b2c53cd76da5f1ace74a20f (diff)
parent57bc29c64a546fc1dc9a14f0d19a1e30fb5948f0 (diff)
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Merge pull request #3282 from nakengelhardt/verific_loop_rams
verific: allow memories to be inferred in loops
Diffstat (limited to 'frontends')
-rw-r--r--frontends/verific/verific.cc1
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 44196a310..b53bad7da 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2548,6 +2548,7 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
+ RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
#ifdef VERIFIC_VHDL_SUPPORT
RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);