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| author | Claire Xen <claire@clairexen.net> | 2021-11-10 20:24:00 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-11-10 20:24:00 +0100 |
| commit | a6c90c9772c2377ad56999e0d57a2514a8fd33dc (patch) | |
| tree | 91148723e25fde4205eec017ab9231f1ed5392c7 /frontends | |
| parent | 4699ddcc1b8e0726821d455bd4d98346d77dc150 (diff) | |
| parent | 15a35f5584977605e685d2a92126a337a474ae89 (diff) | |
| download | yosys-a6c90c9772c2377ad56999e0d57a2514a8fd33dc.tar.gz yosys-a6c90c9772c2377ad56999e0d57a2514a8fd33dc.tar.bz2 yosys-a6c90c9772c2377ad56999e0d57a2514a8fd33dc.zip | |
Merge pull request #3075 from YosysHQ/micko/verific_mem_size
No need to allocate more memory than used
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5a75b52af..47020f105 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1143,7 +1143,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se module->memories[memory->name] = memory; int number_of_bits = net->Size(); - number_of_bits = 1 << ceil_log2(number_of_bits); int bits_in_word = number_of_bits; FOREACH_PORTREF_OF_NET(net, si, pr) { if (pr->GetInst()->Type() == OPER_READ_PORT) { |