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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-11 07:25:52 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-11 07:25:52 +0200 |
| commit | 9112850800a92ed0e330d8470e1273116d78ba14 (patch) | |
| tree | c09bc1be5d109b3270f217614b21f9ef3ca3490d /frontends | |
| parent | fd3d5cefad89a396c9807bf3b8dc7349c1a765f1 (diff) | |
| parent | 6a29e1f5b7e8ac36fcf8c5f00c509ebeaa5257e5 (diff) | |
| download | yosys-9112850800a92ed0e330d8470e1273116d78ba14.tar.gz yosys-9112850800a92ed0e330d8470e1273116d78ba14.tar.bz2 yosys-9112850800a92ed0e330d8470e1273116d78ba14.zip | |
Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
write_verilog: write RTLIL::Sa aka - as Verilog ?
Diffstat (limited to 'frontends')
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