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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 07:58:11 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-08 07:58:11 -0700 |
| commit | 61d7f1997ba7e3098acc25694accdd0ff25b8ab1 (patch) | |
| tree | 9f61784ace2ff54c0f6cd3705804f13af41f964c /frontends | |
| parent | 3414ee1e3fe37d4bf383621542828d4fc8fc987f (diff) | |
| parent | 8bf45f34c4d7143c58acde2544603cde443ad142 (diff) | |
| download | yosys-61d7f1997ba7e3098acc25694accdd0ff25b8ab1.tar.gz yosys-61d7f1997ba7e3098acc25694accdd0ff25b8ab1.tar.bz2 yosys-61d7f1997ba7e3098acc25694accdd0ff25b8ab1.zip | |
Merge pull request #1266 from YosysHQ/eddie/ice40_full_adder
Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 943466ee3..c8ca6d164 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1172,7 +1172,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump if (design->has((*it)->str)) { RTLIL::Module *existing_mod = design->module((*it)->str); - if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { + if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) { log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", (*it)->str.c_str()); } else if (nooverwrite) { log("Ignoring re-definition of module `%s' at %s:%d.\n", |