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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-12 17:54:07 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-12 23:41:27 +0200 |
| commit | 347dd01c2f7dff6e8222c5f9d360f84a17c937b5 (patch) | |
| tree | 2ce79cc1ddda483a78510e7cfe717dc14bbd62ab /frontends | |
| parent | b33744b03ab8c8188e45656722d4a28c173ec67c (diff) | |
| download | yosys-347dd01c2f7dff6e8222c5f9d360f84a17c937b5.tar.gz yosys-347dd01c2f7dff6e8222c5f9d360f84a17c937b5.tar.bz2 yosys-347dd01c2f7dff6e8222c5f9d360f84a17c937b5.zip | |
xilinx: Fix srl regression.
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9. Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
Diffstat (limited to 'frontends')
0 files changed, 0 insertions, 0 deletions