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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-08-10 14:37:36 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-10 14:37:36 +0200 |
| commit | 0b0e01e211d4fa466f29ff25e8d8a37feeda47f7 (patch) | |
| tree | 885509824294c17444dec928d4f80f06a16af57c /frontends | |
| parent | 51f67e55f257e905bc7589a7f529efcd191172f4 (diff) | |
| parent | b76c72056b37d8f2b84948cbdc302b149577e648 (diff) | |
| download | yosys-0b0e01e211d4fa466f29ff25e8d8a37feeda47f7.tar.gz yosys-0b0e01e211d4fa466f29ff25e8d8a37feeda47f7.tar.bz2 yosys-0b0e01e211d4fa466f29ff25e8d8a37feeda47f7.zip | |
Merge pull request #3443 from YosysHQ/micko/resetall_undefineall
resetall does not affect text defines, but undefineall does
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/preproc.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 883531e78..e33b0a2c3 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -961,6 +961,11 @@ frontend_verilog_preproc(std::istream &f, } if (tok == "`resetall") { + default_nettype_wire = true; + continue; + } + + if (tok == "`undefineall" && sv_mode) { defines.clear(); global_defines_cache.clear(); continue; |