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| author | whitequark <whitequark@whitequark.org> | 2020-04-21 14:49:36 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-21 15:27:19 +0000 |
| commit | 06985c3afdba579d0bba266bb6daba0101358ad5 (patch) | |
| tree | 1d27be1d2228304c1831f9601413038f71e48704 /frontends | |
| parent | 12c5e9275c115104896d3c53f0bbdf3fc0c6f37d (diff) | |
| download | yosys-06985c3afdba579d0bba266bb6daba0101358ad5.tar.gz yosys-06985c3afdba579d0bba266bb6daba0101358ad5.tar.bz2 yosys-06985c3afdba579d0bba266bb6daba0101358ad5.zip | |
cxxrtl: unbuffer module input wires.
Module input wires are never set by the module, so it is unnecessary
to buffer them. Although important for all inputs, this is especially
critical for clocks, since after this commit, hierarchy levels no
longer add delta cycles. As a result, Minerva SRAM SoC runs ~73%
faster when flattened, and ~264% (!!) faster when hierarchical.
Diffstat (limited to 'frontends')
0 files changed, 0 insertions, 0 deletions