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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 16:09:50 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 16:09:50 +0200 |
| commit | a03297a7df6c729bc13f629412ae020eb05f7c64 (patch) | |
| tree | af4204ca69c9dd17c358ad2db80d707599141101 /frontends/vhdl2verilog | |
| parent | 55521c085ae1ec735d3cffb80a9880b3cb3e8bca (diff) | |
| download | yosys-a03297a7df6c729bc13f629412ae020eb05f7c64.tar.gz yosys-a03297a7df6c729bc13f629412ae020eb05f7c64.tar.bz2 yosys-a03297a7df6c729bc13f629412ae020eb05f7c64.zip | |
Set results of out-of-bounds static bit/part select to undef
Diffstat (limited to 'frontends/vhdl2verilog')
0 files changed, 0 insertions, 0 deletions