diff options
| author | Clifford Wolf <clifford@clifford.at> | 2016-11-01 10:03:13 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-11-01 10:03:13 +0100 |
| commit | 1e3c2bff72fdba41af5ea3efe083a6c1236c5a56 (patch) | |
| tree | aceec08d5505c687b2328661c00dc5d62ee14894 /frontends/vhdl2verilog | |
| parent | d9d38eeedba7d650ff80e2b364f2f40e9ff1673b (diff) | |
| download | yosys-1e3c2bff72fdba41af5ea3efe083a6c1236c5a56.tar.gz yosys-1e3c2bff72fdba41af5ea3efe083a6c1236c5a56.tar.bz2 yosys-1e3c2bff72fdba41af5ea3efe083a6c1236c5a56.zip | |
Added support for (single-clock) transparent memories to bram tests
Diffstat (limited to 'frontends/vhdl2verilog')
0 files changed, 0 insertions, 0 deletions