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| author | Clifford Wolf <clifford@clifford.at> | 2014-03-01 17:47:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-03-01 17:47:19 +0100 |
| commit | 04999f4af0f6e5c46843d9212abb0c962f533cca (patch) | |
| tree | 14d34f14f538edd04b95cc9eaec2bc9eea7db858 /frontends/vhdl2verilog | |
| parent | 9e9998433616f438cb0185519bb5b7f8e1a8f543 (diff) | |
| download | yosys-04999f4af0f6e5c46843d9212abb0c962f533cca.tar.gz yosys-04999f4af0f6e5c46843d9212abb0c962f533cca.tar.bz2 yosys-04999f4af0f6e5c46843d9212abb0c962f533cca.zip | |
Fixed vhdl2verilog help message
Diffstat (limited to 'frontends/vhdl2verilog')
| -rw-r--r-- | frontends/vhdl2verilog/vhdl2verilog.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc index 9e9953ced..367e63fe0 100644 --- a/frontends/vhdl2verilog/vhdl2verilog.cc +++ b/frontends/vhdl2verilog/vhdl2verilog.cc @@ -35,9 +35,8 @@ struct Vhdl2verilogPass : public Pass { log("\n"); log(" vhdl2verilog [options] <vhdl-file>..\n"); log("\n"); - log("This pass looks for subcircuits that are isomorphic to any of the modules\n"); - log("in the given map file and replaces them with instances of this modules. The\n"); - log("map file can be a verilog source file (*.v) or an ilang file (*.il).\n"); + log("This command reads VHDL source files using the 'vhdl2verilog' tool and the\n"); + log("Yosys Verilog frontend.\n"); log("\n"); log(" -out <out_file>\n"); log(" do not import the vhdl2verilog output. instead write it to the\n"); |