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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-17 02:41:59 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-17 02:41:59 +0200 |
| commit | f5c0ed6c79010df60cdb7ab3ea4c26ed3d61e2f1 (patch) | |
| tree | ab369735abd33351b464ff2bc56df13ee6c37290 /frontends/verilog | |
| parent | 96e7abad48c942452f247267f219d38be902f804 (diff) | |
| download | yosys-f5c0ed6c79010df60cdb7ab3ea4c26ed3d61e2f1.tar.gz yosys-f5c0ed6c79010df60cdb7ab3ea4c26ed3d61e2f1.tar.bz2 yosys-f5c0ed6c79010df60cdb7ab3ea4c26ed3d61e2f1.zip | |
Fixed detection of major wires in opt_clean
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions