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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-15 14:20:10 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-15 14:20:10 +0200 |
| commit | ed32760d4ae8aff3f90a762e0388ef40744b9b22 (patch) | |
| tree | 955a8bb57bef5d251772eb8e269592d8a979b192 /frontends/verilog | |
| parent | 67b10262975340e0b53f8d1072ac2e1c1f087fb1 (diff) | |
| parent | 7e5801beedf63a713386433672429dbc607819c7 (diff) | |
| download | yosys-ed32760d4ae8aff3f90a762e0388ef40744b9b22.tar.gz yosys-ed32760d4ae8aff3f90a762e0388ef40744b9b22.tar.bz2 yosys-ed32760d4ae8aff3f90a762e0388ef40744b9b22.zip | |
Merge pull request #573 from cr1901/msys-64
Add support for 64-bit builds using msys2 environment, use msys-provided `libpthread`.
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions