Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin

2 files changed, 27 insertions, 7 deletions

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index dea22ee8a..7e107dc26 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -490,13 +490,17 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
 			}
 			while (newline_count-- > 0)
 				return_char('\n');
-			// printf("define: >>%s<< -> >>%s<<\n", name.c_str(), value.c_str());
-			defines_map[name] = value;
-			if (state == 2)
-				defines_with_args.insert(name);
-			else
-				defines_with_args.erase(name);
-			global_defines_cache[name] = std::pair<std::string, bool>(value, state == 2);
+			if (strchr("abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789", name[0])) {
+				// printf("define: >>%s<< -> >>%s<<\n", name.c_str(), value.c_str());
+				defines_map[name] = value;
+				if (state == 2)
+					defines_with_args.insert(name);
+				else
+					defines_with_args.erase(name);
+				global_defines_cache[name] = std::pair<std::string, bool>(value, state == 2);
+			} else {
+				log_file_error(filename, 0, "Invalid name for macro definition: >>%s<<.\n", name.c_str());
+			}
 			continue;
 		}
 
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 0e2bead6f..058d750c3 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -553,6 +553,12 @@ struct VerilogDefines : public Pass {
 		log("    -Uname[=definition]\n");
 		log("        undefine the preprocessor symbol 'name'\n");
 		log("\n");
+		log("    -reset\n");
+		log("        clear list of defined preprocessor symbols\n");
+		log("\n");
+		log("    -list\n");
+		log("        list currently defined preprocessor symbols\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
@@ -588,6 +594,16 @@ struct VerilogDefines : public Pass {
 				design->verilog_defines.erase(name);
 				continue;
 			}
+			if (arg == "-reset") {
+				design->verilog_defines.clear();
+				continue;
+			}
+			if (arg == "-list") {
+				for (auto &it : design->verilog_defines) {
+					log("`define %s%s %s\n", it.first.c_str(), it.second.second ? "()" : "", it.second.first.c_str());
+				}
+				continue;
+			}
 			break;
 		}