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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-25 13:07:15 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-25 13:07:15 +0100 |
| commit | dac0842d61b5e3ee63d6f8b87225cde82a763768 (patch) | |
| tree | 0339095b3a795b0bebc76add6a55fc8444037b24 /frontends/verilog | |
| parent | 5f1d0b1024981b6ede2988bf8c5812b37c87d0e9 (diff) | |
| download | yosys-dac0842d61b5e3ee63d6f8b87225cde82a763768.tar.gz yosys-dac0842d61b5e3ee63d6f8b87225cde82a763768.tar.bz2 yosys-dac0842d61b5e3ee63d6f8b87225cde82a763768.zip | |
Add $live and $fair support to AIGER back-end.
Diffstat (limited to 'frontends/verilog')
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