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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-05-23 12:52:13 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-04 19:45:10 +0200 |
| commit | 83cde2d02ba06bbd4014858983ac324bf44cb6c6 (patch) | |
| tree | b999b0fc1a813b7683d85ba63b0cfd129e1d18b2 /frontends/verilog | |
| parent | a9b61080a409d3ad2c8ff4a9bbef9ba1c9c1d194 (diff) | |
| download | yosys-83cde2d02ba06bbd4014858983ac324bf44cb6c6.tar.gz yosys-83cde2d02ba06bbd4014858983ac324bf44cb6c6.tar.bz2 yosys-83cde2d02ba06bbd4014858983ac324bf44cb6c6.zip | |
intel_alm: ABC9 sequential optimisations
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions