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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-20 11:41:57 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-20 13:24:36 +0200 |
| commit | 7b98e46ac352e625be2d8da9b12e7252ed5179d5 (patch) | |
| tree | 3bad42cdef76d76df713046d2063c2946ad5940d /frontends/verilog | |
| parent | 8819493db4e2a02cef5d0ee751ff56605db5995b (diff) | |
| download | yosys-7b98e46ac352e625be2d8da9b12e7252ed5179d5.tar.gz yosys-7b98e46ac352e625be2d8da9b12e7252ed5179d5.tar.bz2 yosys-7b98e46ac352e625be2d8da9b12e7252ed5179d5.zip | |
Added removing of always inactive cells to "share" pass
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions