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| author | David Shah <dave@ds0.me> | 2019-10-01 13:46:36 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-10-01 13:46:36 +0100 |
| commit | 7a1538cd36b45fd3c397dd0414de37af768ad89e (patch) | |
| tree | 2cd1a465a436a344c65ec8201e52a4334fabb84b /frontends/verilog | |
| parent | d963e8c2c6207ad98d48dc528922ad58c030173f (diff) | |
| download | yosys-7a1538cd36b45fd3c397dd0414de37af768ad89e.tar.gz yosys-7a1538cd36b45fd3c397dd0414de37af768ad89e.tar.bz2 yosys-7a1538cd36b45fd3c397dd0414de37af768ad89e.zip | |
ecp5: Add support for mapping 36-bit wide PDP BRAMs
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions