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| author | Rick Altherr <kc8apf@kc8apf.net> | 2016-01-30 19:26:46 -0800 |
|---|---|---|
| committer | Rick Altherr <kc8apf@kc8apf.net> | 2016-01-31 09:20:16 -0800 |
| commit | 34969d41405a1ad418b82caa394f880ea0f6243f (patch) | |
| tree | 4acb3f252cac0f57f446d3c41c1dc737069c1b0d /frontends/verilog | |
| parent | cd3e1095b0c77e3a58feff259b7612e9701f6ce4 (diff) | |
| download | yosys-34969d41405a1ad418b82caa394f880ea0f6243f.tar.gz yosys-34969d41405a1ad418b82caa394f880ea0f6243f.tar.bz2 yosys-34969d41405a1ad418b82caa394f880ea0f6243f.zip | |
genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree()
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions