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| author | Clifford Wolf <clifford@clifford.at> | 2019-11-13 13:41:16 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-11-13 13:41:16 +0100 |
| commit | 07c854b7afc793a589df06c7fce200260378b379 (patch) | |
| tree | b5a5471c6ea60444b80076e7cf1cd5eaa4affb53 /frontends/verilog | |
| parent | 6e332161dbdc399c41041cebaf83cbb156b331a7 (diff) | |
| download | yosys-07c854b7afc793a589df06c7fce200260378b379.tar.gz yosys-07c854b7afc793a589df06c7fce200260378b379.tar.bz2 yosys-07c854b7afc793a589df06c7fce200260378b379.zip | |
Add "autoname" pass and use it in "synth_ice40"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions