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| author | clairexen <claire@symbioticeda.com> | 2020-07-01 16:35:27 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-01 16:35:27 +0200 |
| commit | b1707407a0912fe44ecf83f6f8e64b13a1c4daee (patch) | |
| tree | d1408b0745e1d552a9e27edf58468c89515ca04e /frontends/verilog/verilog_parser.y | |
| parent | 2b0f6e24e24770b6bab2180bb2c6cc560eb8ec5a (diff) | |
| parent | 83c595aaacb9617aa00439626f2ea5bf9777c7e9 (diff) | |
| download | yosys-b1707407a0912fe44ecf83f6f8e64b13a1c4daee.tar.gz yosys-b1707407a0912fe44ecf83f6f8e64b13a1c4daee.tar.bz2 yosys-b1707407a0912fe44ecf83f6f8e64b13a1c4daee.zip | |
Merge pull request #2138 from boqwxp/qbfsat-oflag
qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
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