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| author | whitequark <whitequark@whitequark.org> | 2020-04-10 14:51:01 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-10 14:51:01 +0000 |
| commit | 93ef516d919b40ace2099bc7586bfda8648f0757 (patch) | |
| tree | ab7e043e1c9d5cd1e6ff5258fd1e6709081200a0 /frontends/verilog/verilog_parser.y | |
| parent | 93c6c6779861d7b41fae1b87d54790e0a9555b80 (diff) | |
| parent | 763401fc827d444bfef5a10ff658a3bf7e89b76c (diff) | |
| download | yosys-93ef516d919b40ace2099bc7586bfda8648f0757.tar.gz yosys-93ef516d919b40ace2099bc7586bfda8648f0757.tar.bz2 yosys-93ef516d919b40ace2099bc7586bfda8648f0757.zip | |
Merge pull request #1603 from whitequark/ice40-ram_style
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
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