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author | Clifford Wolf <clifford@clifford.at> | 2017-04-28 18:54:53 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-04-28 18:57:53 +0200 |
commit | 3bbac5c1414e3b59b8d965711f2f424aff3c762a (patch) | |
tree | ab2e232dccaa764718ee8a0cade7b3ab3c24ca84 /frontends/verilog/verilog_parser.y | |
parent | f0db8ffdbcd64560739639dfde078c14f9939604 (diff) | |
download | yosys-3bbac5c1414e3b59b8d965711f2f424aff3c762a.tar.gz yosys-3bbac5c1414e3b59b8d965711f2f424aff3c762a.tar.bz2 yosys-3bbac5c1414e3b59b8d965711f2f424aff3c762a.zip |
Fix equiv_simple, old behavior now available with "equiv_simple -short"
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
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