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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-05-18 18:15:03 +0200 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-05-19 01:42:40 +0200 |
| commit | aee439360bba642dcbffe5b803aa9a994b11d183 (patch) | |
| tree | a5c15b4a6172ea3ff651f88174fff7d5269ad1c2 /frontends/verilog/verilog_lexer.l | |
| parent | 2d573a0ff680eb9f38358943fbf134f765ba1451 (diff) | |
| download | yosys-aee439360bba642dcbffe5b803aa9a994b11d183.tar.gz yosys-aee439360bba642dcbffe5b803aa9a994b11d183.tar.bz2 yosys-aee439360bba642dcbffe5b803aa9a994b11d183.zip | |
Add force_downto and force_upto wire attributes.
Fixes #2058.
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
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