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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 20:42:34 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 21:38:23 +0200 |
| commit | 3514c92dc42644d64dca2167c05096d10891de69 (patch) | |
| tree | 61b294a7b812d93496f2d9551742dc7fa1a7b21e /frontends/verilog/verilog_lexer.l | |
| parent | e6b078d156f8690ab06d342da9be9af02cbcc3aa (diff) | |
| download | yosys-3514c92dc42644d64dca2167c05096d10891de69.tar.gz yosys-3514c92dc42644d64dca2167c05096d10891de69.tar.bz2 yosys-3514c92dc42644d64dca2167c05096d10891de69.zip | |
mem/extract_rdff: Add alternate transparency handling.
When extracting read register from a transparent port that has an
enable, reset, or initial value, the usual trick of putting a register
on the address instead of data doesn't work. In this case, create soft
transparency logic instead.
When transparency masks land, this will also be used to handle ports
that are transparent to only a subset of write ports.
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
0 files changed, 0 insertions, 0 deletions