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authorClifford Wolf <clifford@clifford.at>2015-07-30 21:43:41 +0200
committerClifford Wolf <clifford@clifford.at>2015-07-30 21:43:41 +0200
commit3860c9a9f23104bd54e0000b74624e45c77a8ab3 (patch)
tree86a217141408973d5e59894930a9a8872c047e39 /frontends/verilog/verilog_frontend.h
parenteac0bcd7d34840ae29386d766659f6e70f1cf44d (diff)
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Fixed flatten $meminit handling
Diffstat (limited to 'frontends/verilog/verilog_frontend.h')
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#!/usr/bin/python3

from pyosys import libyosys as ys

import matplotlib.pyplot as plt
import numpy as np

design = ys.Design()
ys.run_pass("read_verilog ../../tests/simple/fiedler-cooley.v", design);
ys.run_pass("prep", design)
ys.run_pass("opt -full", design)

cell_stats = {}
for module in design.selected_whole_modules_warn():
  for cell in module.selected_cells():
    if cell.type.str() in cell_stats:
      cell_stats[cell.type.str()] += 1
    else:
      cell_stats[cell.type.str()] = 1
plt.bar(range(len(cell_stats)), height = list(cell_stats.values()),align='center')
plt.xticks(range(len(cell_stats)), list(cell_stats.keys()))
plt.show()