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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-30 17:00:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-30 17:00:34 +0200 |
| commit | d9d50b0b0c4da21c9bf2b0f1499297368b808491 (patch) | |
| tree | 6a926310738ae81a1b98f74066e79f423310b33b /frontends/verilog/verilog_frontend.cc | |
| parent | 727eec04c53c6863b18883a5afd7cee1cb52a157 (diff) | |
| parent | 58e991a0eb36f0a5a23170e6818338efa7445a44 (diff) | |
| download | yosys-d9d50b0b0c4da21c9bf2b0f1499297368b808491.tar.gz yosys-d9d50b0b0c4da21c9bf2b0f1499297368b808491.tar.bz2 yosys-d9d50b0b0c4da21c9bf2b0f1499297368b808491.zip | |
Merge branch 'master' into eddie/refactor_synth_xilinx
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index ed6ce2ecb..9e624d355 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -242,8 +242,6 @@ struct VerilogFrontend : public Frontend { nowb_mode = false; default_nettype_wire = true; - log_header(design, "Executing Verilog-2005 frontend.\n"); - args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end()); size_t argidx; @@ -415,6 +413,8 @@ struct VerilogFrontend : public Frontend { } extra_args(f, filename, args, argidx); + log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str()); + log("Parsing %s%s input from `%s' to AST representation.\n", formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str()); |