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authorClifford Wolf <clifford@clifford.at>2019-06-19 13:53:07 +0200
committerGitHub <noreply@github.com>2019-06-19 13:53:07 +0200
commit5a1f1caa44fb3f4427813acab61aaecc06bae7ba (patch)
tree3cceea7d49a6ae44e5ab765e0bd11fecfee6b47b /frontends/verilog/verilog_frontend.cc
parentc330379870a48209534807d1c021ce2a20ccf880 (diff)
parentfa5fc3f6afd9eb27c1f52244b60cbeb77aa2e26c (diff)
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Merge pull request #1105 from YosysHQ/clifford/fixlogicinit
Improve handling of initial/default values
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