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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 18:09:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 18:09:38 -0700 |
| commit | 31ff0d8ef529a1ddfa37e4b68017e4e433399da7 (patch) | |
| tree | 921a3a801a4e7bc9d8998b0aa7f21506db7881e6 /frontends/verilog/verilog_frontend.cc | |
| parent | e97178a888cebc6acacb8f8f2c68d4f9743a9284 (diff) | |
| parent | f86d153cef724af9d30e4139783a7e14d7ba0a19 (diff) | |
| download | yosys-31ff0d8ef529a1ddfa37e4b68017e4e433399da7.tar.gz yosys-31ff0d8ef529a1ddfa37e4b68017e4e433399da7.tar.bz2 yosys-31ff0d8ef529a1ddfa37e4b68017e4e433399da7.zip | |
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index ed6ce2ecb..9e624d355 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -242,8 +242,6 @@ struct VerilogFrontend : public Frontend { nowb_mode = false; default_nettype_wire = true; - log_header(design, "Executing Verilog-2005 frontend.\n"); - args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end()); size_t argidx; @@ -415,6 +413,8 @@ struct VerilogFrontend : public Frontend { } extra_args(f, filename, args, argidx); + log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str()); + log("Parsing %s%s input from `%s' to AST representation.\n", formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str()); |