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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 15:13:18 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 15:13:18 -0800 |
| commit | 2a54fa41c40969841ba0574ba725caa436b0212f (patch) | |
| tree | 1dbf518fc73dbe253612bdb5e466c50b78bce44b /frontends/verilog/verilog_frontend.cc | |
| parent | 6b9f90de789b1d0daf93ac1d2b608b057e7ca272 (diff) | |
| parent | c03b6a3e9cab9fc05b2d5b256676f5ddc6c2d763 (diff) | |
| download | yosys-2a54fa41c40969841ba0574ba725caa436b0212f.tar.gz yosys-2a54fa41c40969841ba0574ba725caa436b0212f.tar.bz2 yosys-2a54fa41c40969841ba0574ba725caa436b0212f.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 0e2bead6f..058d750c3 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -553,6 +553,12 @@ struct VerilogDefines : public Pass { log(" -Uname[=definition]\n"); log(" undefine the preprocessor symbol 'name'\n"); log("\n"); + log(" -reset\n"); + log(" clear list of defined preprocessor symbols\n"); + log("\n"); + log(" -list\n"); + log(" list currently defined preprocessor symbols\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { @@ -588,6 +594,16 @@ struct VerilogDefines : public Pass { design->verilog_defines.erase(name); continue; } + if (arg == "-reset") { + design->verilog_defines.clear(); + continue; + } + if (arg == "-list") { + for (auto &it : design->verilog_defines) { + log("`define %s%s %s\n", it.first.c_str(), it.second.second ? "()" : "", it.second.first.c_str()); + } + continue; + } break; } |