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| author | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2019-12-13 10:17:05 -0300 |
|---|---|---|
| committer | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2019-12-13 10:17:05 -0300 |
| commit | e9dc2759c414bdc8ab663fd5c8350b40b099b456 (patch) | |
| tree | 45193a6e47536347b92f42e78d1cf4d773d37f67 /frontends/verilog/preproc.cc | |
| parent | 9ab1feeaf11adb6b675ac4034e246cb137d07db9 (diff) | |
| download | yosys-e9dc2759c414bdc8ab663fd5c8350b40b099b456.tar.gz yosys-e9dc2759c414bdc8ab663fd5c8350b40b099b456.tar.bz2 yosys-e9dc2759c414bdc8ab663fd5c8350b40b099b456.zip | |
Fixed some missing "verilog_" in documentation
Diffstat (limited to 'frontends/verilog/preproc.cc')
| -rw-r--r-- | frontends/verilog/preproc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 7e107dc26..161253a99 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -28,7 +28,7 @@ * * Ad-hoc implementation of a Verilog preprocessor. The directives `define, * `include, `ifdef, `ifndef, `else and `endif are handled here. All other - * directives are handled by the lexer (see lexer.l). + * directives are handled by the lexer (see verilog_lexer.l). * */ |