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| author | Archie <ac11018@ic.ac.uk> | 2022-08-21 17:18:20 -0500 |
|---|---|---|
| committer | Archie <ac11018@ic.ac.uk> | 2022-08-21 17:18:20 -0500 |
| commit | db73f3c26b2768f93c7573b7c7d74b1cc7a0756d (patch) | |
| tree | 81696fd98770e519aea96fe3a6e40bcc3b3a4360 /frontends/verilog/preproc.cc | |
| parent | e7e8e3b0f65ea1ebfcf04bffd0d9ba90f8e0d7fe (diff) | |
| parent | 029c2785e810fda0ccc5abbb6057af760f2fc6f3 (diff) | |
| download | yosys-db73f3c26b2768f93c7573b7c7d74b1cc7a0756d.tar.gz yosys-db73f3c26b2768f93c7573b7c7d74b1cc7a0756d.tar.bz2 yosys-db73f3c26b2768f93c7573b7c7d74b1cc7a0756d.zip | |
Merge branch 'master' of https://github.com/ALGCDG/yosys
Diffstat (limited to 'frontends/verilog/preproc.cc')
| -rw-r--r-- | frontends/verilog/preproc.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 883531e78..e33b0a2c3 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -961,6 +961,11 @@ frontend_verilog_preproc(std::istream &f, } if (tok == "`resetall") { + default_nettype_wire = true; + continue; + } + + if (tok == "`undefineall" && sv_mode) { defines.clear(); global_defines_cache.clear(); continue; |