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| author | Clifford Wolf <clifford@clifford.at> | 2017-03-04 23:41:54 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-03-04 23:41:54 +0100 |
| commit | c8553539866128279897336795f00248eb527ffa (patch) | |
| tree | bd65478263b5388c56825769719dc1aee408269c /frontends/verilog/preproc.cc | |
| parent | a6ca28276e3786ba3d756f46d7804a6dcf1e5b11 (diff) | |
| download | yosys-c8553539866128279897336795f00248eb527ffa.tar.gz yosys-c8553539866128279897336795f00248eb527ffa.tar.bz2 yosys-c8553539866128279897336795f00248eb527ffa.zip | |
Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msg
Diffstat (limited to 'frontends/verilog/preproc.cc')
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