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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-13 03:39:23 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-13 03:39:23 -0700 |
| commit | ab3917d0791874bab845ca74203c5aaa2ec842d2 (patch) | |
| tree | 2ad7c104f5dd890a3e7cbc1e383cc048bfcafd5f /frontends/verilog/Makefile.inc | |
| parent | 463f7100665b38ca346f3919a65ff7626c24c91c (diff) | |
| download | yosys-ab3917d0791874bab845ca74203c5aaa2ec842d2.tar.gz yosys-ab3917d0791874bab845ca74203c5aaa2ec842d2.tar.bz2 yosys-ab3917d0791874bab845ca74203c5aaa2ec842d2.zip | |
Error out if enable > dbits
Diffstat (limited to 'frontends/verilog/Makefile.inc')
0 files changed, 0 insertions, 0 deletions