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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-27 14:22:21 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-08-27 14:22:21 +0200 |
| commit | ddc1761f1a443ea9560c67cfc126160ba7254a39 (patch) | |
| tree | 024214903fdf08578b38478be42b820abc09140b /frontends/verilog/.gitignore | |
| parent | 9e845bd25460d7b8287cf3ea5147040689940f49 (diff) | |
| download | yosys-ddc1761f1a443ea9560c67cfc126160ba7254a39.tar.gz yosys-ddc1761f1a443ea9560c67cfc126160ba7254a39.tar.bz2 yosys-ddc1761f1a443ea9560c67cfc126160ba7254a39.zip | |
Add "make coverage"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog/.gitignore')
| -rw-r--r-- | frontends/verilog/.gitignore | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/.gitignore b/frontends/verilog/.gitignore index 1d4ae9e5c..aadbcdcdd 100644 --- a/frontends/verilog/.gitignore +++ b/frontends/verilog/.gitignore @@ -1,4 +1,4 @@ verilog_lexer.cc verilog_parser.output verilog_parser.tab.cc -verilog_parser.tab.h +verilog_parser.tab.hh |