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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-27 14:27:51 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-27 14:27:51 +0200 |
| commit | 0f38008ed34e36e798f521b4b6d4fea89ae31a3b (patch) | |
| tree | 2fc23463121715ae0fb602ac9bf871ee9dd82c5e /frontends/verilog/.gitignore | |
| parent | 974b6a947c822e9f1a5e67c4847c98b923d30398 (diff) | |
| download | yosys-0f38008ed34e36e798f521b4b6d4fea89ae31a3b.tar.gz yosys-0f38008ed34e36e798f521b4b6d4fea89ae31a3b.tar.bz2 yosys-0f38008ed34e36e798f521b4b6d4fea89ae31a3b.zip | |
Added "design" command (-reset, -save, -load)
Diffstat (limited to 'frontends/verilog/.gitignore')
0 files changed, 0 insertions, 0 deletions