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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-22 15:08:30 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-22 15:08:30 +0200 |
| commit | b6bd12fade053b5f9d00ce4c710d29ae6fb3d3b5 (patch) | |
| tree | a67f55bea02c740debbf71537c3da6d2e60d5ff0 /frontends/verific | |
| parent | 024ba310ecffa9dde47bbe66d82eab91d1f0c609 (diff) | |
| download | yosys-b6bd12fade053b5f9d00ce4c710d29ae6fb3d3b5.tar.gz yosys-b6bd12fade053b5f9d00ce4c710d29ae6fb3d3b5.tar.bz2 yosys-b6bd12fade053b5f9d00ce4c710d29ae6fb3d3b5.zip | |
Add error for cell output ports that are connected to constants
Diffstat (limited to 'frontends/verific')
0 files changed, 0 insertions, 0 deletions