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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-01 12:51:49 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-01 12:51:49 +0100 |
| commit | 6c00e064e2024b7b41d3c32ed4cf7f0f6857506b (patch) | |
| tree | 203c04c4c90718d32007d9cf07584ca0590f5a32 /frontends/verific | |
| parent | 9af40faa0b60e2c0717f36888c1e19183e40a88c (diff) | |
| download | yosys-6c00e064e2024b7b41d3c32ed4cf7f0f6857506b.tar.gz yosys-6c00e064e2024b7b41d3c32ed4cf7f0f6857506b.tar.bz2 yosys-6c00e064e2024b7b41d3c32ed4cf7f0f6857506b.zip | |
Fix single-bit $stable handling in verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verific.cc | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index fa1640050..09c379f19 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1150,6 +1150,28 @@ struct VerificImporter continue; } + if (inst->Type() == PRIM_SVA_STABLE && !mode_nosva) + { + VerificClockEdge clock_edge(this, inst->GetInput2()->Driver()); + + SigSpec sig_d = net_map_at(inst->GetInput1()); + SigSpec sig_o = net_map_at(inst->GetOutput()); + SigSpec sig_q = module->addWire(NEW_ID); + + if (verbose) { + log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clock_edge.posedge ? "pos" : "neg", + log_signal(sig_d), log_signal(sig_q), log_signal(clock_edge.clock_sig)); + log(" XNOR with A=%s, B=%s, Y=%s.\n", + log_signal(sig_d), log_signal(sig_q), log_signal(sig_o)); + } + + module->addDff(NEW_ID, clock_edge.clock_sig, sig_d, sig_q, clock_edge.posedge); + module->addXnor(NEW_ID, sig_d, sig_q, sig_o); + + if (!mode_keep) + continue; + } + if (inst->Type() == PRIM_SVA_PAST && !mode_nosva) { VerificClockEdge clock_edge(this, inst->GetInput2()->Driver()); |