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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-01-17 12:58:08 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2023-01-17 12:58:08 +0100 |
| commit | 6574553189fb6ccb5d00a0c043671a625672b3d3 (patch) | |
| tree | 57e3212ee75493d9f4939c9f9029b95880367a76 /frontends/verific | |
| parent | 956c4e485a9463863f60c4dd03372db3fa8332a4 (diff) | |
| download | yosys-6574553189fb6ccb5d00a0c043671a625672b3d3.tar.gz yosys-6574553189fb6ccb5d00a0c043671a625672b3d3.tar.bz2 yosys-6574553189fb6ccb5d00a0c043671a625672b3d3.zip | |
Fixes for some of clang scan-build detected issues
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verific.cc | 10 | ||||
| -rw-r--r-- | frontends/verific/verificsva.cc | 4 |
2 files changed, 8 insertions, 6 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index a93d79c80..8898c4597 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2317,8 +2317,8 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin const char *lib_name = (prefix) ? prefix->GetName() : 0 ; if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; } - veri_module = (lib && module_name) ? lib->GetModule(module_name->GetName(), 1) : 0; - top = veri_module->GetName(); + if (lib && module_name) + top = lib->GetModule(module_name->GetName(), 1)->GetName(); } } @@ -2344,6 +2344,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin int i; FOREACH_ARRAY_ITEM(netlists, i, nl) { + if (!nl) continue; if (!top.empty() && nl->CellBaseName() != top) continue; nl->AddAtt(new Att(" \\top", NULL)); @@ -3297,8 +3298,8 @@ struct VerificPass : public Pass { const char *lib_name = (prefix) ? prefix->GetName() : 0 ; if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; } - veri_module = (lib && module_name) ? lib->GetModule(module_name->GetName(), 1) : 0; - top_mod_names.insert(veri_module->GetName()); + if (lib && module_name) + top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName()); } } else { log("Adding Verilog module '%s' to elaboration queue.\n", name); @@ -3333,6 +3334,7 @@ struct VerificPass : public Pass { int i; FOREACH_ARRAY_ITEM(netlists, i, nl) { + if (!nl) continue; if (!top_mod_names.count(nl->CellBaseName())) continue; nl->AddAtt(new Att(" \\top", NULL)); diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 12bac2a3d..986a98643 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1777,7 +1777,7 @@ struct VerificSvaImporter if (mode_assert) c = module->addLive(root_name, sig_a_q, sig_en_q); if (mode_assume) c = module->addFair(root_name, sig_a_q, sig_en_q); - importer->import_attributes(c->attributes, root); + if (c) importer->import_attributes(c->attributes, root); return; } @@ -1822,7 +1822,7 @@ struct VerificSvaImporter if (mode_assume) c = module->addAssume(root_name, sig_a_q, sig_en_q); if (mode_cover) c = module->addCover(root_name, sig_a_q, sig_en_q); - importer->import_attributes(c->attributes, root); + if (c) importer->import_attributes(c->attributes, root); } } catch (ParserErrorException) |