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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-26 18:28:55 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-26 18:28:55 +0200 |
| commit | 649bb9374f84d653bc724a53fa631ff334861cd0 (patch) | |
| tree | 5e743e8f0b803b791559e01fe74eb8cc0bae16b7 /frontends/verific | |
| parent | 530040ba6f0877fe91814b582749fda28d31c928 (diff) | |
| download | yosys-649bb9374f84d653bc724a53fa631ff334861cd0.tar.gz yosys-649bb9374f84d653bc724a53fa631ff334861cd0.tar.bz2 yosys-649bb9374f84d653bc724a53fa631ff334861cd0.zip | |
Add "opt_expr -fine" feature to remove neutral bits from reduce and logic operators
Diffstat (limited to 'frontends/verific')
0 files changed, 0 insertions, 0 deletions