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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-26 15:20:27 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-26 15:20:27 +0100 |
| commit | 2aeb4d4e1231807144e62930ce9c95795265f6b3 (patch) | |
| tree | 65213ef6a8e9023e3f628500dc92e05be48172d0 /frontends/verific | |
| parent | 9cd9f5fc7895ec1e7d16026772e068c19fbc73bd (diff) | |
| download | yosys-2aeb4d4e1231807144e62930ce9c95795265f6b3.tar.gz yosys-2aeb4d4e1231807144e62930ce9c95795265f6b3.tar.bz2 yosys-2aeb4d4e1231807144e62930ce9c95795265f6b3.zip | |
Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verific.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 4c28d4c43..1a16f7508 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -569,6 +569,19 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr return true; } + if (inst->Type() == OPER_SELECTOR) + { + module->addPmux(inst_name, State::S0, IN2, IN1, net_map_at(inst->GetOutput())); + return true; + } + + if (inst->Type() == OPER_WIDE_SELECTOR) + { + SigSpec out = OUT; + module->addPmux(inst_name, SigSpec(State::S0, GetSize(out)), IN2, IN1, out); + return true; + } + if (inst->Type() == OPER_WIDE_TRI) { module->addMux(inst_name, RTLIL::SigSpec(RTLIL::State::Sz, inst->OutputSize()), IN, net_map_at(inst->GetControl()), OUT); return true; |