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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-13 20:23:19 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-13 20:23:19 +0200 |
| commit | 1954c78ea7b6ddc732ac4dc9f02a0d0cbc104a64 (patch) | |
| tree | 06e2f8a12488ed8cdc78229f83961321e6bf779c /frontends/verific | |
| parent | e7a3c47cc793eaacff3b3bf0e996944f6963a7a8 (diff) | |
| download | yosys-1954c78ea7b6ddc732ac4dc9f02a0d0cbc104a64.tar.gz yosys-1954c78ea7b6ddc732ac4dc9f02a0d0cbc104a64.tar.bz2 yosys-1954c78ea7b6ddc732ac4dc9f02a0d0cbc104a64.zip | |
Add "verific -vlog-libdir"
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verific.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index f8c1dcd0a..77594b8cf 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1856,6 +1856,12 @@ struct VerificPass : public Pass { log("Add Verilog include directories.\n"); log("\n"); log("\n"); + log(" verific -vlog-libdir <directory>..\n"); + log("\n"); + log("Add Verilog library directories. Verific will search in this directories to\n"); + log("find undefined modules.\n"); + log("\n"); + log("\n"); log(" verific -vlog-define <macro>[=<value>]..\n"); log("\n"); log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n"); @@ -1942,6 +1948,12 @@ struct VerificPass : public Pass { goto check_error; } + if (GetSize(args) > argidx && args[argidx] == "-vlog-libdir") { + for (argidx++; argidx < GetSize(args); argidx++) + veri_file::AddYDir(args[argidx].c_str()); + goto check_error; + } + if (GetSize(args) > argidx && args[argidx] == "-vlog-define") { for (argidx++; argidx < GetSize(args); argidx++) { string name = args[argidx]; |