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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-20 17:45:22 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-20 17:45:22 +0100 |
| commit | 17583b6a2175bf509d6a233e5684a183af54f48c (patch) | |
| tree | 349aa6e15a76cea692d4c0832f4a7e95ac76baaa /frontends/verific | |
| parent | f2cfe73d74a5be195ee704c99f472dc454015a66 (diff) | |
| download | yosys-17583b6a2175bf509d6a233e5684a183af54f48c.tar.gz yosys-17583b6a2175bf509d6a233e5684a183af54f48c.tar.bz2 yosys-17583b6a2175bf509d6a233e5684a183af54f48c.zip | |
Add support for mockup clock signals in yosys-smtbmc vcd output
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verific')
0 files changed, 0 insertions, 0 deletions